What is CMOS 2.0?

What is CMOS 2.0?

With the emergence of CMOS 2.0, the field of chip design is on the brink of revolution.

CMOS, the silicon logic technology behind smaller transistors and faster computers for decades, is entering a new phase. CMOS uses two paired transistors to limit the power consumption of circuits. In this new phase, "CMOS 2.0," this aspect will not change, but the way processors and other complex CMOS chips are manufactured will change. Julien Ryckaert, Vice President of Logic Technology at Imec, a nanoelectronics research center based in Belgium, introduced to IEEE Spectrum the direction in which things are heading.

Why is CMOS entering a new phase?

Julien Ryckaert: CMOS was the technological choice for building microprocessors in the 1960s. It made transistors and interconnects smaller to make them work better for 60, 70 years. But this situation has started to collapse.

Ryckaert: For years, people have been making systems on a chip (SoC) like CPUs and GPUs increasingly complex. That is, they are integrating more and more operations into the same silicon chip. This makes sense because moving data on a silicon chip is much more efficient than moving data between chips in a computer.

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For a long time, the scaling down of CMOS transistors and interconnects has made all these operations work better. But now, building an entire SoC, just by scaling up devices and interconnects to make it better, is becoming increasingly difficult. For example, the scalability of SRAM is no longer the same as that of logic.Challenges of Modern CMOS Scaling

With the advancement of semiconductor technology, modern CMOS scaling faces complex challenges. The downscaling of transistors to enhance performance encounters obstacles such as power consumption, heat dissipation, and quantum effects. Balancing these factors is crucial for maintaining the pace of innovation in electronic devices.

Short Channel Effect (SCE)

The short channel effect (SCE) refers to the detrimental effects that occur in metal-oxide-semiconductor field-effect transistors (MOSFETs) when the device dimensions reach 1µm. These effects are primarily due to the reduction in physical gate length and the increase in the electric field at the channel's drain end.

As the gate length decreases, the gate's control over the channel weakens, leading to various adverse effects such as increased leakage current, reduced carrier mobility, and diminished threshold voltage control.

Historically, researchers have focused on reducing the physical gate oxide thickness and designing doping profiles for the source, drain, and channel to mitigate these effects. However, the semiconductor field has introduced new materials and device architectures, such as strained channels, high-k dielectric metal gates (HKMG), silicon on insulator (SOI), and fin field-effect transistors (FinFETs), to actively suppress the short channel effect (SCE) and address other adverse impacts.

Limitations of Traditional Scaling Efforts

The continuous expansion of CMOS technology has encountered obstacles, primarily due to the limitations of traditional scaling efforts. The latest International Roadmap for Devices and Systems (IRDS) indicates that the scaling for low-power (LP) and high-performance (HP) applications will stagnate at physical gate lengths of 14nm and 12nm, respectively, for sub-5nm technology nodes, presenting significant challenges for further scaling.Device Electrostatics and Variability

Improving device electrostatic characteristics and addressing the variability issues of ultra-scaled MOSFETs have become key challenges in modern CMOS scaling.

The term "device electrostatics" here refers to the quantification and enhancement of the scalability of FETs. The natural length, denoted by λ, quantifies the scalability of an FET by capturing the steepness of the potential change from the source or drain to the channel. Effective modulation of the channel potential is crucial for controlling the mobile charge carrier population, and addressing these electrostatic challenges is vital for scalability.

Tapering Layered Extension FET Scaling Scenario. The tap works similarly to an FET, using a knob or gate to control the flow of water or charge carriers from a source to a drain through a channel. Different forms of diverters represent different scaling schemes. The natural length is denoted by λ.

What is the solution?

Ryckaert: Ultimately, Moore's Law is not about providing smaller transistors and interconnections, but about achieving more functionality per unit area. What you start to see is the breaking down of certain functions, such as logic and SRAM, building them on separate chips using technologies that can best leverage their individual strengths, and then reintegrating them using advanced 3D packaging techniques. You can connect two functions built on different substrates and achieve communication efficiency between these two functions that rivals the efficiency when these functions are on the same substrate. This is what we refer to as the evolution of intelligent disassembly or system technology co-optimization.Is that CMOS 2.0?

Ryckaert: What we are doing in CMOS 2.0 is further pushing this idea, through finer granularity functional decomposition and stacking of more chips. The first sign of CMOS 2.0 is the upcoming backside power supply network. On today's chips, all interconnections (including those that transmit data and those that provide power) are located on the front side of the silicon (above the transistors). These two types of interconnections have different functions and different requirements, but so far they have had to coexist in a compromised way. The backside power supply moves the power transmission interconnections to below the silicon, essentially turning the chip into an active transistor layer sandwiched between two interconnection stacks, each with different functions.

Do transistors and interconnections in CMOS 2.0 still need to maintain size scaling?

Ryckaert: Yes, because at some point in that stack, you will still have a layer that still needs more transistors per unit area. But now, because you have eliminated all the other constraints it once had, you can let that layer scale very well with the technology that is very suitable for it.

The future of CMOS 2.0

The potential applications of CMOS 2.0 are very broad, covering various industries:

Artificial Intelligence (AI): Neuromorphic chips can significantly accelerate the development of artificial intelligence, enable faster training of complex algorithms, and pave the way for more advanced AI applications.

Internet of Things (IoT): Its miniaturization and energy efficiency advantages can promote the development of smaller, more energy-efficient IoT devices, fostering the development of an interconnected world.High-Performance Computing (HPC): The advanced chip architecture it supports can unleash new levels of computational capabilities, facilitating complex scientific simulations and data analysis.

Consumer Electronics: The potential of denser, more efficient chips can lead to more stylish and powerful smartphones, laptops, and other consumer devices.

Conclusion

CMOS 2.0 is the pinnacle of imec's vision for future chip design, encompassing full 3D chip design. We have already seen AMD's second-generation 3D V-Cache memory stacking, which stacks L3 memory on top of the processor to increase memory capacity, but imec envisions the entire cache hierarchy contained within its own layers, including L1, L2, and L3 caches vertically stacked on their own chips above the transistors that make up the processing core. Each level of cache would be created using the transistors best suited for that task, which means older nodes for SRAM, becoming more important as the rate of SRAM scaling begins to slow down significantly. The scaling down of SRAM has led to caches consuming a higher proportion of the chip, resulting in increased cost per MB and hindering chip manufacturers from using larger caches. Therefore, the cost reduction brought about by migrating to a lower-density cache node through 3D stacking could also lead to caches being much larger than we have seen in the past. If implemented correctly, 3D stacking can also help mitigate latency issues associated with larger caches.

The CMOS 2.0 revolution opens a transformative chapter in the history of chip design. However, by adopting new materials, device structures, and design paradigms, it has the potential to address current limitations, unlock new functionalities, and propel the technology sector into a brighter future. As research and development in this field continue to evolve, the true impact of CMOS 2.0 has not yet been fully realized, but its potential to shape the future of technology is undeniable.

With the advent of CMOS 2.0, the field of chip design is on the brink of revolution. Moreover, this groundbreaking approach is expected to redefine the boundaries of semiconductor technology, offering a glimpse into a future of limitless computational capabilities. It can be said that this paradigm shift presents a more complex technological reality. How quickly will EDA tools evolve? Will the costs and complexities of partitioning become prohibitive? Is the thermal performance of the CMOS 2.0 platform controllable? Only time will provide the answers. To quote the German philosopher and revolutionary Friedrich Engels: "No one knows for certain the revolution he is making." In the meantime, this is precisely what makes these times so fascinating. Exploring these uncharted territories requires close cooperation and joint innovation across the entire semiconductor ecosystem. What is at stake is not Moore's Law itself, but the ability it represents to foster economic growth, scientific advancement, and sustainable innovation.

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